Non-volatile semiconductor memory cells using a floating gate to store charges thereon and memory arrays of such non-volatile memory cells formed in a semiconductor substrate are well known in the art. Typically, such floating gate memory cells have been of the split gate type, or stacked gate type.
It is also known to form memory cell elements over non-planar portions of the substrate. For example, U.S. Pat. No. 5,780,341 (Ogura) discloses a number of memory device configurations that includes a step channel formed in the substrate surface. While the purpose of the step channel is to inject hot electrons more efficiently onto the floating gate, these memory device designs are still deficient in that it is difficult to optimize the size and formation of the memory cell elements as well the necessary operational parameters needed for efficient and reliable operation.
The use of three gates in a non-volatile memory cell is also well known in the art. See for example U.S. Pat. Nos. 5,856,943 or 6,091,104.
Finally, self-aligned methods to form non-volatile split gate floating gate memory cells are also well known. See U.S. Pat. No. 6,329,685.
Erasure of charges on a floating gate through the mechanism of poly-to-poly tunneling of electrons through Fowler-Nordheim tunneling is also well known in the art. See U.S. Pat. No. 5,029,130, whose disclosure is incorporated herein by reference in its entirety.
Thus, it is one object of the present invention to create a self-aligned method to make a non-planar split gate floating non-volatile memory cell, and an array of such cells, in which the cell has three gates: a floating gate, a control gate and an erase gate, wherein charges are removed from the floating gate to the erase gate through the mechanism of Fowler-Nordheim tunneling.